Symbolically Parametrized Modules#664
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… that ROHD modules can generate parametrized SV.
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Description & Motivation
A limitation in the partial adoption path for ROHD is the case where a ROHD module is meant to be instantiated in a larger non-ROHD (ex: SystemVerilog) context and the larger context expects the ROHD module to be parametrizable at its build/synth time (i.e., after ROHD has generated its output representation for that context).
One option is to put the larger context into a generator framework but that can be a non-starter in some cases.
Hence, the goal is to enable ROHD to generate output that can be parametrized by the output context's build/synth flow. In this PR, we focus only on SystemVerilog.
Related Issue(s)
N/A
Testing
Many new unit tests as well as updates to existing unit tests with new test cases as needed.
Backwards-compatibility
The intent is for this to be fully backwards compatible. I.e., this is a new, additive construct.
Documentation
Dedicated documentation provided for this feature.